Comparison of Static and Dynamic Faults in 65nm Memory Technology

This paper presents single-cell dynamic fault models for deep-submicron semiconductor memories together with their associated tests (test primitives). The test primitives are evaluated industrially, together with the traditional tests, using 65nm technology 131 Kbytes embedded SRAMs. A comparison between static faults and dynamic faults is presented and the results are reported; they show the increasing importance of dynamic faults, and the exceptional effectiveness of using back-to-back operations (with complementary data values) along bit lines during memory testing. The paper also presents a systematic approach to distinguish between the different detected faults and therefore evaluate the importance and the occurrence frequency of such faults. Keywords—static faults, dynamic faults, fault primitives, fault models, memory tests, fault coverage.